Adaptive Block Pinning for Multi-core Architectures

Difference between speed of processor and memory is increasing with advent of every new technology. Chip Multi Processors (CMP) have further increased the load on the memory hierarchy. So it has become important to manage on-chip memory judiciously to reduce average memory access time. The previous research has shown that it is better to have a shared cache at the last level of on-chip memory hierarchy. Sharing last level of cache gives rise to a new category of cache misses; those were not present in uniprocessor, called “inter-processor misses”. This paper proposes a technique to eliminate inter-processor misses by giving replacement ownership of a block to a processor who brought it into the cache. This reduction in interprocessor misses, which constitutes 40% of over all misses, will result in performance improvement. Also two different ways of relinquishing the ownership of a block are being proposed, so that if some other processor, other than owner, can make use of the block in a more efficient way, ownership will be transferred to the